Job Id E1975121
Job Title Senior Design verificaton Engineer
Post Date 07/29/2019
Company - Division Qualcomm Atheros Inc - Qualcomm Atheros
Job Area Engineering - Hardware
Location China - Shanghai
Job Overview Acts as a tech lead on small to large projects and owns team deliverables of the project. Define testbench infrastructure using System Verilog, UVM and Formal. Assist in complete verification of high performance, high speed, low power ASIC. Work closely with system architect and design managers to architect a new design verification environment and produce high quality verification closure. Guide the development of comprehensive, flexible, and portable block to chip level testbench, detailed test plans and coverage closure. Infrastructure work including developing scripts, methodologies and tools for efficiency and quality improvements.
Minimum Qualifications Bachelor's degree in Science, Engineering, or related field.
5+ years ASIC design, verification, or related work experience.

Preferred Qualifications Bachelor's degree in Electrical Engineering, Computer Science, or Computer Engineering. 8+ years ASIC design, verification, or related work experience. 2+ years experience with architecture and design tools. 2+ years experience with scripting tools and programming languages. 2+ years experience with design verification methods. 1+ years of work experience in a role requiring interaction with senior leadership (e.g., Director level and above). UVM verification methodology Assertion and formal to support coverage-driven verification. Experience on lead SOC verification is Plus.
Education Requirements NA
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