Job Id E1975775
Job Title ASIC Design Engineer
Post Date 09/08/2019
Company - Division Qualcomm Atheros Inc - Qualcomm Atheros
Job Area Engineering - Hardware
Location China - Shanghai
Job Overview The Digital Design Engineer will be responsible for designing our wireless and SOC ASIC's. You will work closely with our architecture/algorithm engineers to explore ideas for next generation products and then develop RTL to turn these ideas into customer solutions. Duties/Responsibilities: Chip features specification and RTL design Lint, CDC, UPF generation, Synthesis, verification, timing sign-off. FPGA emulation, lab validation and debugging.
Minimum Qualifications Bachelor's degree in Science, Engineering, or related field.
2+ years ASIC design, verification, or related work experience.

Preferred Qualifications Qualifications: MS in Electrical/Electronics Engineering At least 3 years hands on experience with specification, micro-architecture, design, RTL coding, verification Proficient in the use of industry standard languages and flows for RTL coding, synthesis, functional verification, timing analysis, power estimation and scripting. Nice to have a proven record of delivering successful ASICs from functional specification to the final product. One or more advantages as following are highly desirable: Hands on experience in WLAN MAC design and familiar with IEEE802.11 standard; A strong background in digital communication, signal processing and networking protocols; IC Design experiences in wireless communications; Experiences with ARM/DSP, NoC/AXI/AHB bus and External memory controller development. Excellent team and interpersonal skills Clear written and verbal communication. Good communication skills in English. Desired to have cross-functional experience interacting with software, verification, and physical design teams. Skills/Experience: Must be proficient in RTL coding, Lint/CDC checking, logic synthesis, block/chip level timing analysis and familiar with low power design flow. Good knowledge of IC design backend flows. Experiences in IC life-cycle from conception, design, verification, top-level netlist with pads to tape-out, chip-testing and mass-production is a plus. Familiar with pre-silicon and post-silicon validation of ASIC designs is a plus FPGA or embedded SW skill is a plus.
Education Requirements NA
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