Job Id E1978847
Job Title SOC Design Verification Engineer(New Graduate)
Post Date 11/25/2019
Company - Division Qualcomm Atheros Inc - Qualcomm Atheros
Job Area Engineering - Hardware
Location China - Shanghai
Job Overview Develop reusable block-level and system-level ASIC testbenches using Systemverilog -Develop new ASIC verification environments to support ASIC development. -Maintain existing ASIC verification environments. -Define and develop application tests required to verify ASICs meet functional and performance goals. -Define and implement functional/code coverage plans. -Develop testing and regression methodologies for new verification flow. -Develop/maintain/enhance environment tools/scripts/makefiles.
Minimum Qualifications Bachelor's degree in Science, Engineering, or related field.
Preferred Qualifications Proven verification and superior debugging skills in large ASIC designs -Rich experience with Specman E or System Verilog ,VMM/UVM -Rich ASIC design skills is highly desirable -Knowledge of low power verification is a big plus -Experience with one or more scripting languages(TCL/Perl/Python) is desired -Strong written and verbal communication skills -Adaptable to evolving customer requirement
Education Requirements MS in Electrical engineering, Electrical and Computer engineering, or Computer Science, MS preferred
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