Job Id E1978928
Job Title Design Verification Engineer(all levels)
Post Date 11/27/2019
Company - Division Qualcomm Atheros Inc - Qualcomm Atheros
Job Area Engineering - Verification
Location China - Shanghai
Job Overview Define testbench infrastructure using System Verilog, UVM and Formal. Assist in complete verification of high performance, high speed, low power ASIC. Work closely with system architect and design team to architect a new design verification environment and produce high quality verification closure. Guide the development of comprehensive, flexible, and portable block to chip level testbench, detailed test plans and coverage closure. Infrastructure work including developing scripts, methodologies and tools for efficiency and quality improvements.
Minimum Qualifications Bachelor's degree in Science, Engineering, or related field.
2+ years ASIC design, verification, or related work experience.
Preferred Qualifications Strong verification skills including a good knowledge and understanding of different verification methodologies: random vs directed testing full chip vs module-level performance vs function error & drop handling Past experience of successfully technically guiding complex, high speed design verification. Experience with the following areas in design and verification: Expert in Advanced constrained-random functional verification methodology such as UVM/OVM/VMM and/or SV Assertion. Expert in industry I/O interface such as PCIe, USB, SERDES, Ethernet, etc. Good skills in using script language such as Perl, Makefile, etc. Low power verification with UPF. Experienced in mix signal simulation is a big plus. Self-motivated, good communicator, quick learner and good team player. Display positive attitude and demonstrate flexibility in day-to-day work.
Education Requirements Education Requirements MS/EE or CS with 3+ years of relevant experience.

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